| |
| 17 Apr 2008 09:43:09 |
| Dave |
| Survey: FPGA PCB layout |
Does anybody out there have a good methodology for determining your optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? The brute force method is fairly maddening. I'd be curious to hear if anybody has any 'tricks of the trade' here. Also, just out of curiosity, how many of you do your own PCB layout, versus farming it out? It would certainly save us a lot of money to buy the tools and do it ourselves, but it seems like laying out a board out well requires quite a bit of experience, especially a 6-8 layer board with high pin count FPGA's. We're just setting up a hardware shop here, and although I've been doing FPGA and board schematics design for a while, it's always been at a larger company with resources to farm the layout out, and we never did anything high-speed to really worry about the board layout too much. Thanks in advance for your opinions. Dave |
| 17 Apr 2008 17:40:54 |
| qrk |
| Re: Survey: FPGA PCB layout |
On Thu, 17 Apr 2008 09:43:09 -0700 (PDT), Dave <dhschetz@gmail.com > wrote: >Does anybody out there have a good methodology for determining your >optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >The brute force method is fairly maddening. I'd be curious to hear if >anybody has any 'tricks of the trade' here. > >Also, just out of curiosity, how many of you do your own PCB layout, >versus farming it out? It would certainly save us a lot of money to >buy the tools and do it ourselves, but it seems like laying out a >board out well requires quite a bit of experience, especially a 6-8 >layer board with high pin count FPGA's. > >We're just setting up a hardware shop here, and although I've been >doing FPGA and board schematics design for a while, it's always been >at a larger company with resources to farm the layout out, and we >never did anything high-speed to really worry about the board layout >too much. Thanks in advance for your opinions. > >Dave Sure wish there was a slick way of doing FPGA pinouts. I usually use graph paper and figure out the FPGA pinout to other parts to minimize routing snarls. I do pcb layouts on my own and other folks designs. Our boards have high-speed routing, switching power supplies, and high-gain analog stuff; sometimes all on the same board. Unless the service bureau has someone who understands how to lay out such circuitry and place sensitive analog stuff near digital junk, it is more trouble to farm out than do it yourself if you want the board to work on the first cut. Doing your own layout will take a lot of learning to master the PCB layout program and what your board vendor can handle. It will take 5 to 10 complicated boards to become mildly proficient at layout. I don't know about saving cost. Your time may be better spent doing other activities rather than learning about layout and doing the layouts. The upside to doing your own layout - you control the whole design from start to finish. If you have a challenging layout, you'll have a much higher probability of having a working board on the first try which has hidden savings (getting to market earlier <- less troubleshooting + less respins). --- Mark |
| 17 Apr 2008 10:50:36 |
| Joerg |
| Re: Survey: FPGA PCB layout |
qrk wrote: > On Thu, 17 Apr 2008 09:43:09 -0700 (PDT), Dave <dhschetz@gmail.com> > wrote: > >> Does anybody out there have a good methodology for determining your >> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >> The brute force method is fairly maddening. I'd be curious to hear if >> anybody has any 'tricks of the trade' here. >> >> Also, just out of curiosity, how many of you do your own PCB layout, >> versus farming it out? It would certainly save us a lot of money to >> buy the tools and do it ourselves, but it seems like laying out a >> board out well requires quite a bit of experience, especially a 6-8 >> layer board with high pin count FPGA's. >> >> We're just setting up a hardware shop here, and although I've been >> doing FPGA and board schematics design for a while, it's always been >> at a larger company with resources to farm the layout out, and we >> never did anything high-speed to really worry about the board layout >> too much. Thanks in advance for your opinions. >> >> Dave > > Sure wish there was a slick way of doing FPGA pinouts. I usually use > graph paper and figure out the FPGA pinout to other parts to minimize > routing snarls. > > I do pcb layouts on my own and other folks designs. Our boards have > high-speed routing, switching power supplies, and high-gain analog > stuff; sometimes all on the same board. Unless the service bureau has > someone who understands how to lay out such circuitry and place > sensitive analog stuff near digital junk, it is more trouble to farm > out than do it yourself if you want the board to work on the first > cut. > Or find a good layouter and develop a long-term business relationship. My layouter knows just from looking at a schematic which areas are critical. He's a lot older than I am and that is probably one of the reasons why his stuff works without much assistance from me. Nothing can replace a few decades of experience. > Doing your own layout will take a lot of learning to master the PCB > layout program and what your board vendor can handle. It will take 5 > to 10 complicated boards to become mildly proficient at layout. I > don't know about saving cost. Your time may be better spent doing > other activities rather than learning about layout and doing the > layouts. ... Yep, that's why I usually do not do my own layouts. Occassionally I route a small portion of a circuit and send that to my layouter. No DRC or anything, just to show him how I'd like it done. > ... The upside to doing your own layout - you control the whole > design from start to finish. If you have a challenging layout, you'll > have a much higher probability of having a working board on the first > try which has hidden savings (getting to market earlier <- less > troubleshooting + less respins). > > --- > Mark -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. |
| 17 Apr 2008 11:36:32 |
| John Adair |
| Re: Survey: FPGA PCB layout |
Dave We are slightly unusual in that we started as FPGA design house and now probably better known for our boards even though we do an awful lot of internal FPGA design still. A lot of board layout is just common sense. Having a plan of how it all fits together - not just placement but routing runs between chips usually pays great dividends. Having someone who understands both the FPGA and the pcb layout is usually a great advantage as it allows tradeoffs to be made easily and generally ends up with with a better board. Swaping I/Os as you layout will give a much better results. That all said we are still learning on our pcb design skills even after producing development boards for nearly 5 years and I can still say generally that every new board we do is technically better than the previous one we did. Your first board will probably take a long time especially if it as in any way complex. Our first development board (Broaddown2 for the interested) that we released took about 800hrs of man effort. We would do that same board now in probably less than 1/3 of that time now. So in summary you have the difficult decision whether to invest time in learning the trade, making mistakes along the way, and possibly getting better boards versus the direct cost of using someone experienced and reducing the risks of a good enough to ship first layout. Very few people achieve boards that are good enough to ship as practical production boards as first revisions and if you do that you are doing well. Wire mods etc in production cost lots. I'm know of some designs done by customers themselves that have gone to 7 versions due to mistakes in layout. That's not cheap and really hits timescales. I'm proud to say my team have delivered over 50% of our development boards to production, to ship at 1st issue, but that is definately unusual in boards of that level of complexity. Board can be an enjoyable task but it's not for the impatient. John Adair Enterpoint Ltd. On Apr 17, 5:43=A0pm, Dave <dhsch...@gmail.com > wrote: > Does anybody out there have a good methodology for determining your > optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? > The brute force method is fairly maddening. I'd be curious to hear if > anybody has any 'tricks of the trade' here. > > Also, just out of curiosity, how many of you do your own PCB layout, > versus farming it out? It would certainly save us a lot of money to > buy the tools and do it ourselves, but it seems like laying out a > board out well requires quite a bit of experience, especially a 6-8 > layer board with high pin count FPGA's. > > We're just setting up a hardware shop here, and although I've been > doing FPGA and board schematics design for a while, it's always been > at a larger company with resources to farm the layout out, and we > never did anything high-speed to really worry about the board layout > too much. Thanks in advance for your opinions. > > Dave |
| 17 Apr 2008 17:13:27 |
| Steve |
| Re: Survey: FPGA PCB layout |
"Joerg" <notthisjoergsch@removethispacbell.net > wrote in message news:U5MNj.6956$GE1.6193@nlpi061.nbdc.sbc.com... > qrk wrote: >> On Thu, 17 Apr 2008 09:43:09 -0700 (PDT), Dave <dhschetz@gmail.com> >> wrote: >> >>> Does anybody out there have a good methodology for determining your >>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >>> The brute force method is fairly maddening. I'd be curious to hear if >>> anybody has any 'tricks of the trade' here. >>> >>> Also, just out of curiosity, how many of you do your own PCB layout, >>> versus farming it out? It would certainly save us a lot of money to >>> buy the tools and do it ourselves, but it seems like laying out a >>> board out well requires quite a bit of experience, especially a 6-8 >>> layer board with high pin count FPGA's. >>> >>> We're just setting up a hardware shop here, and although I've been >>> doing FPGA and board schematics design for a while, it's always been >>> at a larger company with resources to farm the layout out, and we >>> never did anything high-speed to really worry about the board layout >>> too much. Thanks in advance for your opinions. >>> >>> Dave >> >> Sure wish there was a slick way of doing FPGA pinouts. I usually use >> graph paper and figure out the FPGA pinout to other parts to minimize >> routing snarls. >> >> I do pcb layouts on my own and other folks designs. Our boards have >> high-speed routing, switching power supplies, and high-gain analog >> stuff; sometimes all on the same board. Unless the service bureau has >> someone who understands how to lay out such circuitry and place >> sensitive analog stuff near digital junk, it is more trouble to farm >> out than do it yourself if you want the board to work on the first >> cut. >> > > Or find a good layouter and develop a long-term business relationship. My > layouter knows just from looking at a schematic which areas are critical. > He's a lot older than I am and that is probably one of the reasons why his > stuff works without much assistance from me. Nothing can replace a few > decades of experience. > > >> Doing your own layout will take a lot of learning to master the PCB >> layout program and what your board vendor can handle. It will take 5 >> to 10 complicated boards to become mildly proficient at layout. I >> don't know about saving cost. Your time may be better spent doing >> other activities rather than learning about layout and doing the >> layouts. ... > > > Yep, that's why I usually do not do my own layouts. Occassionally I route > a small portion of a circuit and send that to my layouter. No DRC or > anything, just to show him how I'd like it done. > > >> ... The upside to doing your own layout - you control the whole >> design from start to finish. If you have a challenging layout, you'll >> have a much higher probability of having a working board on the first >> try which has hidden savings (getting to market earlier <- less >> troubleshooting + less respins). >> >> --- >> Mark > > > -- > Regards, Joerg > > http://www.analogconsultants.com/ > > "gmail" domain blocked because of excessive spam. > Use another domain or send PM. I agree with Joerg. Good high speed or mixed signal PCB layout is a career choice, and we electrical engineers already chose our career. A good layout requires someone who understands not just the software package, but the details of how the manufacturing operation is going to proceed, what the limits of the processes are, what the assembly operations require of the board, and is anal about things like footprint libraries and solder mask clearances and a thousand other details that I'm only partially aware of. The more complex your design, the more critical these things become. I have two good local outfits for farming out boards. For complex stuff, they know I'll come to their place and sit next to the designer for a good bit of the initial placement. While we are doing placement, we are also discussing critical nets, routing paths, layer usage, etc. That gives us direct face to face communication and avoids spending lots of time trying to write/draw everything in gory detail (which gets ignored or misunderstood a lot of the time). That investment pays big dividends in schedule and board performance. Don't be fooled by the relatively low cost of the software. That's not where the big costs are. I once laid off my entire PCB layout department and sent all the work outside, because although my employees all knew how to use the software, none of them could tell me what their completion date would be, or how many hours it would take, and they certainly weren't interested in meeting schedules. The outside sources would commit to a cost and a delivery date. And we already knew they could meet our performance objectives. Fixed price contracts are great motivators. Missing an engineering test window, or slipping a production schedule because of a layout delay can be enormously expensive. Of course, if I had let my engineers do their own layouts, the motivation would have been present, but the technical proficiency would not. How proficient can anyone become if they only do layout a few times a year? Also, on many projects engineers use the layout period for other important things like documentation, test procedures, writing test code, etc. Doing your own layout serializes these tasks and will stretch your schedule. So my advice is to keep doing what you have been doing. Its far more likely that its the cheapest approach, even though you occasionally have to write a big check. Steve |
| 17 Apr 2008 15:15:34 |
| Dave |
| Re: Survey: FPGA PCB layout |
On Apr 17, 5:13 pm, "Steve" <sjbur...@comcast.net > wrote: > "Joerg" <notthisjoerg...@removethispacbell.net> wrote in message > > news:U5MNj.6956$GE1.6193@nlpi061.nbdc.sbc.com... > > > > > qrk wrote: > >> On Thu, 17 Apr 2008 09:43:09 -0700 (PDT), Dave <dhsch...@gmail.com> > >> wrote: > > >>> Does anybody out there have a good methodology for determining your > >>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? > >>> The brute force method is fairly maddening. I'd be curious to hear if > >>> anybody has any 'tricks of the trade' here. > > >>> Also, just out of curiosity, how many of you do your own PCB layout, > >>> versus farming it out? It would certainly save us a lot of money to > >>> buy the tools and do it ourselves, but it seems like laying out a > >>> board out well requires quite a bit of experience, especially a 6-8 > >>> layer board with high pin count FPGA's. > > >>> We're just setting up a hardware shop here, and although I've been > >>> doing FPGA and board schematics design for a while, it's always been > >>> at a larger company with resources to farm the layout out, and we > >>> never did anything high-speed to really worry about the board layout > >>> too much. Thanks in advance for your opinions. > > >>> Dave > > >> Sure wish there was a slick way of doing FPGA pinouts. I usually use > >> graph paper and figure out the FPGA pinout to other parts to minimize > >> routing snarls. > > >> I do pcb layouts on my own and other folks designs. Our boards have > >> high-speed routing, switching power supplies, and high-gain analog > >> stuff; sometimes all on the same board. Unless the service bureau has > >> someone who understands how to lay out such circuitry and place > >> sensitive analog stuff near digital junk, it is more trouble to farm > >> out than do it yourself if you want the board to work on the first > >> cut. > > > Or find a good layouter and develop a long-term business relationship. My > > layouter knows just from looking at a schematic which areas are critical. > > He's a lot older than I am and that is probably one of the reasons why his > > stuff works without much assistance from me. Nothing can replace a few > > decades of experience. > > >> Doing your own layout will take a lot of learning to master the PCB > >> layout program and what your board vendor can handle. It will take 5 > >> to 10 complicated boards to become mildly proficient at layout. I > >> don't know about saving cost. Your time may be better spent doing > >> other activities rather than learning about layout and doing the > >> layouts. ... > > > Yep, that's why I usually do not do my own layouts. Occassionally I route > > a small portion of a circuit and send that to my layouter. No DRC or > > anything, just to show him how I'd like it done. > > >> ... The upside to doing your own layout - you control the whole > >> design from start to finish. If you have a challenging layout, you'll > >> have a much higher probability of having a working board on the first > >> try which has hidden savings (getting to market earlier <- less > >> troubleshooting + less respins). > > >> --- > >> Mark > > > -- > > Regards, Joerg > > >http://www.analogconsultants.com/ > > > "gmail" domain blocked because of excessive spam. > > Use another domain or send PM. > > I agree with Joerg. Good high speed or mixed signal PCB layout is a career > choice, and we electrical engineers already chose our career. A good layout > requires someone who understands not just the software package, but the > details of how the manufacturing operation is going to proceed, what the > limits of the processes are, what the assembly operations require of the > board, and is anal about things like footprint libraries and solder mask > clearances and a thousand other details that I'm only partially aware of. > The more complex your design, the more critical these things become. > > I have two good local outfits for farming out boards. For complex stuff, > they know I'll come to their place and sit next to the designer for a good > bit of the initial placement. While we are doing placement, we are also > discussing critical nets, routing paths, layer usage, etc. That gives us > direct face to face communication and avoids spending lots of time trying to > write/draw everything in gory detail (which gets ignored or misunderstood a > lot of the time). That investment pays big dividends in schedule and board > performance. > > Don't be fooled by the relatively low cost of the software. That's not where > the big costs are. > > I once laid off my entire PCB layout department and sent all the work > outside, because although my employees all knew how to use the software, > none of them could tell me what their completion date would be, or how many > hours it would take, and they certainly weren't interested in meeting > schedules. The outside sources would commit to a cost and a delivery date. > And we already knew they could meet our performance objectives. Fixed price > contracts are great motivators. Missing an engineering test window, or > slipping a production schedule because of a layout delay can be enormously > expensive. > > Of course, if I had let my engineers do their own layouts, the motivation > would have been present, but the technical proficiency would not. How > proficient can anyone become if they only do layout a few times a year? > Also, on many projects engineers use the layout period for other important > things like documentation, test procedures, writing test code, etc. Doing > your own layout serializes these tasks and will stretch your schedule. > > So my advice is to keep doing what you have been doing. Its far more likely > that its the cheapest approach, even though you occasionally have to write a > big check. > > Steve I tend to agree with the 'farm-it-out' crowd. Unfortunately, my current employer doesn't want to work with my previous layout people, so I've been trying to search for a new partner. I've found plenty of board fab and assembly places, but not so much on the layout. It made me think that the rest of the world did their own layout. The opinions look pretty split from the replies here, maybe it comes down to how many times you do a layout each year, and how much you enjoy that sort of work. I definitely think it's something you have to do fairly often to keep your chops up. Andy, I'd also like to hear more about your pin-swap FPGA design flow - what tools do that? Also curious about any timing issues that have been caught after the pin-swap. Thank you all very much for the info. If any of you find yourself in the Baltimore area, I owe you a crabcake sandwich and a beer. Dave |
| 17 Apr 2008 18:51:09 |
| Jeff Cunningham |
| Re: Survey: FPGA PCB layout |
Dave wrote: > > I tend to agree with the 'farm-it-out' crowd. Unfortunately, my > current employer doesn't want to work with my previous layout people, > so I've been trying to search for a new partner. I've found plenty of > board fab and assembly places, but not so much on the layout. It made Some of the PCB software vendors have lists on their web site of independent consultants and layout houses that use their software. I went on the Mentor site and found zillions of layout people. -Jeff |
| 17 Apr 2008 16:20:32 |
| Joel Koltner |
| Re: Survey: FPGA PCB layout |
"Dave" <dhschetz@gmail.com > wrote in message news:dfc27fc0-c07f-456c-80cb-b31e867dd253@d1g2000hsg.googlegroups.com... > The opinions > look pretty split from the replies here, maybe it comes down to how > many times you do a layout each year, and how much you enjoy that sort > of work. I definitely think it's something you have to do fairly often > to keep your chops up. I think what you're seeing is that fact that, by sheer volume of products, guys doing relatively low-speed digital stuff completely dominate those doing very low-level analog, RF, microwave, or truly high-speed digital. In the former case, it just doesn't really matter that much how you layout the board. Sure, there are definitely better ways and worse ways, but even up to clock rates pushing 100MHz, for digital stuff I think you can give a guy about an hour of education and he'll be able to make boards work just fine. Another point to keep in mind is that there's a significant difference between being able to design a board well when you're talking relatively small volume production for high-end commercial or military customers where you can afford to just toss in some extra layers and pay for blind or buried vias or tigether tolerances if you're at all unsure of how well your layout skills really are vs. designing a complex board for highly cost-competitive mass-markets. The later requires a lot of skills that are anything but what is commonly taught! (E.g., typically at tech seminars you'll hear people preaching, "throw in a ground plane!" -- an action that saves many an otherwise broken design, but one which might not be possible if your competition has already figured out how to live without one.) I'm a big advocate of giving "technical interviews" to would-be PCB layout guys based on what your needs are. If you're doing, e.g., RF or high-speed digital design, ask them how line impedances change with changes in board and trace dimensions, what near-end and far-end crosstalk look like on a scope, what they think about splitting up ground planes, how they'd route some simple circuits, etc... Usually you can find out pretty quickly what their skills are whether or not they're adequate or if they'd need a bit more hand-holding... which could be fine too, if you have the time and the price is right. > Andy, I'd also like to hear more about your pin-swap FPGA design flow > - what tools do that? It's a common feature in most PCB tools to allow pin (and gate) swapping based on the component's library entry being set up to designate which pins and gates are "swappable." After doing so, most of them will produce a simple ASCII "was-is" text file that list the old pin name and the new one, which can be imported back into a schematic capture program or used to update your FPGA place & route constraints. (PADS will do all this, where Pulsonix unfortunately does pin & gate swapping quite nicely but will only update a Pulsonix schematic "directly" rather than providing you with the option to generate a was-is file.) ---Joel |
| 17 Apr 2008 16:46:55 |
| Joerg |
| Re: Survey: FPGA PCB layout |
Joel Koltner wrote: > "Dave" <dhschetz@gmail.com> wrote in message > news:dfc27fc0-c07f-456c-80cb-b31e867dd253@d1g2000hsg.googlegroups.com... >> The opinions >> look pretty split from the replies here, maybe it comes down to how >> many times you do a layout each year, and how much you enjoy that sort >> of work. I definitely think it's something you have to do fairly often >> to keep your chops up. > > I think what you're seeing is that fact that, by sheer volume of products, > guys doing relatively low-speed digital stuff completely dominate those doing > very low-level analog, RF, microwave, or truly high-speed digital. In the > former case, it just doesn't really matter that much how you layout the board. > Sure, there are definitely better ways and worse ways, but even up to clock > rates pushing 100MHz, for digital stuff I think you can give a guy about an > hour of education and he'll be able to make boards work just fine. > Not anymore. Part of my daily bread is earned salvaging designs where someone thought "Oh, it's just slow stuff". But it ain't grampa's old SN7400 anymore, today's logic chips are fast. Some like the tiny logic chips swing their outputs within very few nanoseconds. Then some unexpected weirdnesses show up. Everyone thinks it's software but in reality crosstalk has manifested itself. Other times the moment of truth cometh at the EMC lab when a thick forrest shows up on the spectrum analyzer. > Another point to keep in mind is that there's a significant difference between > being able to design a board well when you're talking relatively small volume > production for high-end commercial or military customers where you can afford > to just toss in some extra layers and pay for blind or buried vias or tigether > tolerances if you're at all unsure of how well your layout skills really are > vs. designing a complex board for highly cost-competitive mass-markets. The > later requires a lot of skills that are anything but what is commonly taught! > (E.g., typically at tech seminars you'll hear people preaching, "throw in a > ground plane!" -- an action that saves many an otherwise broken design, but > one which might not be possible if your competition has already figured out > how to live without one.) > And don't split that plane. But yes, often one has to make do with two-layer phenolic. That is often true art. BTW does that little switcher work? [...] -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. |
| 17 Apr 2008 17:52:38 |
| Joel Koltner |
| Re: Survey: FPGA PCB layout |
"Joerg" <notthisjoergsch@removethispacbell.net > wrote in message news:ZjRNj.9697$2g1.9469@nlpi068.nbdc.sbc.com... > Not anymore. Part of my daily bread is earned salvaging designs where > someone thought "Oh, it's just slow stuff". But it ain't grampa's old SN7400 > anymore, today's logic chips are fast. OK, ok, good point. Doesn't someone now have a logic family that's purposely been slowed down due to this "problem?" > And don't split that plane. But yes, often one has to make do with two-layer > phenolic. That is often true art. From Thomas Lee (Stanford) in "Planar Microwave Engineering": In extremely low-cost consumer devices (e.g., toys, pocket radios, etc.), an even less expensive board material is not infrequently encountered. Phenolic is often a caramel brown, typically has an "organical chemical" odor, and is remarkably lossy. Although phenolic is occasionally used for RF toys up to 100MHz, it is totally insuitable for serious applications. It is mentioned here simply to answer the question: "What is that cheap, malodorous board made of?" :-) I know, I know, he's living in an ivory tower a bit, but he is one smart cookie. > BTW does that little switcher work? I've had that board back for about a week, although I haven't actually tested out the switcher yet since the DSP guy isn't interested in working with the new (digital) board until the new RF board comes back (and gets tested) as well, which is still a couple weeks out. (There's this "Big Tester Board" that's needed to test the RF board and said BTB has spent something over a week bouncing around engineering getting tweaked/fixed/etc... we'll be paying a premium to actually get it fabbed in time to start testing RF boards at this point, unfortunately :-( .) I can and probably should just put a dummy load on the switcher, turn it on, and see if there's any obvious problems before the DSP guy starts looking at his clock jitter. Tomorrow sounds like a good day for that... ---Joel |
| 18 Apr 2008 01:31:40 |
| Joerg |
| Re: Survey: FPGA PCB layout |
Joel Koltner wrote: > "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message > news:ZjRNj.9697$2g1.9469@nlpi068.nbdc.sbc.com... >> Not anymore. Part of my daily bread is earned salvaging designs where >> someone thought "Oh, it's just slow stuff". But it ain't grampa's old SN7400 >> anymore, today's logic chips are fast. > > OK, ok, good point. Doesn't someone now have a logic family that's purposely > been slowed down due to this "problem?" > There used to be but it's gone. They also had really high threshold voltages and stuff. >> And don't split that plane. But yes, often one has to make do with two-layer >> phenolic. That is often true art. > > From Thomas Lee (Stanford) in "Planar Microwave Engineering": > > In extremely low-cost consumer devices (e.g., toys, pocket radios, etc.), an > even less expensive board material is not infrequently encountered. Phenolic > is often a caramel brown, typically has an "organical chemical" odor, and is > remarkably lossy. Although phenolic is occasionally used for RF toys up to > 100MHz, it is totally insuitable for serious applications. It is mentioned > here simply to answer the question: "What is that cheap, malodorous board made > of?" > > :-) > > I know, I know, he's living in an ivory tower a bit, but he is one smart > cookie. > Errr, well, those sure sound like ivory tower statements. For some reason all the phenolic I ever used has never smelled. Unless something blew up on there, of course, but then FR4 will also let off a nasty stench. The new stuff looks amazingly similar to FR4, not dark brown. Remarkably lossy? Nah. I have proof to the contrary right here in the garage (if it's still there), a VHF/UHF TV splitter and 60ohm to 240ohm transformer where the UHF part is almost completely done in microstrip. Yes, microstrip on phenolic. There may be a fraction of a dB here and there but on short stretches that hardly matters. Usually those things are for outdoors so it's lacquer coated anyway. Phenolic is somewhat hygroscopic so you have to watch out for moisture. Totally insuitable for serious applications? Oh man. Let's see, what have we here? A 418MHz transmitter, several matching networks, a UHF receiver ... all on phenolic. Sometimes I wish that professors had more nose-to-the-grindstone industry work under the belt. I mean real design work where cost is a big factor. Otherwise they are going to tell students they should use Rogers for just about everything ... >> BTW does that little switcher work? > > I've had that board back for about a week, although I haven't actually tested > out the switcher yet since the DSP guy isn't interested in working with the > new (digital) board until the new RF board comes back (and gets tested) as > well, which is still a couple weeks out. (There's this "Big Tester Board" > that's needed to test the RF board and said BTB has spent something over a > week bouncing around engineering getting tweaked/fixed/etc... we'll be paying > a premium to actually get it fabbed in time to start testing RF boards at this > point, unfortunately :-( .) I can and probably should just put a dummy load > on the switcher, turn it on, and see if there's any obvious problems before > the DSP guy starts looking at his clock jitter. Tomorrow sounds like a good > day for that... > That would be good. Gives you a head start just in case there is a surprise ;-) -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. |
| 17 Apr 2008 20:25:05 |
| John Larkin |
| Re: Survey: FPGA PCB layout |
On Thu, 17 Apr 2008 09:43:09 -0700 (PDT), Dave <dhschetz@gmail.com > wrote: >Does anybody out there have a good methodology for determining your >optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >The brute force method is fairly maddening. I'd be curious to hear if >anybody has any 'tricks of the trade' here. What's the brute force method? We preassign most fpga pins for clean, no-crossover routing to other chips. We discuss the general issues, especially placement, with our pcb layout guy and he actually decides which pins go where. Then he back-annotates the schematic and gives us a file we can use to create the fpga pin constraints file. Sometimes bank issues complicate the process, but it works pretty well. > >Also, just out of curiosity, how many of you do your own PCB layout, >versus farming it out? It would certainly save us a lot of money to >buy the tools and do it ourselves, but it seems like laying out a >board out well requires quite a bit of experience, especially a 6-8 >layer board with high pin count FPGA's. We'd never farm it out. We do critical mixed-signal stuff, and need to be near our layout guy constantly. He puts up a version on our server daily at least, and we keep an eye on progress. And we have a lot of mini-meetings to change the rules as needed. Besides, we have evolved some styles (and libraries!) that we couldn't very well transfer to a service bureau. PCB layout is too important to farm out. > >We're just setting up a hardware shop here, and although I've been >doing FPGA and board schematics design for a while, it's always been >at a larger company with resources to farm the layout out, and we >never did anything high-speed to really worry about the board layout >too much. Thanks in advance for your opinions. For really critical stuff, sometimes I'll take over and route that part of the board myself. It's just too hard to communicate exactly what I want. John |
| 18 Apr 2008 07:01:56 |
| Andy Botterill |
| Re: Survey: FPGA PCB layout |
Joerg wrote: > Joel Koltner wrote: > > > Totally insuitable for serious applications? Oh man. Let's see, what > have we here? A 418MHz transmitter, several matching networks, a UHF > receiver ... all on phenolic. Multi ghz RF+matching stuff, analog and some digital will work on an FR4 derivative. > > Sometimes I wish that professors had more nose-to-the-grindstone > industry work under the belt. I mean real design work where cost is a > big factor. Otherwise they are going to tell students they should use > Rogers for just about everything ... Don't forget rogers is not perfect , intolerance to flexing and intolerant of poor soldering techniques. > |
| 18 Apr 2008 00:09:02 |
| David L. Jones |
| Re: Survey: FPGA PCB layout |
On Apr 18, 8:15 am, Dave <dhsch...@gmail.com > wrote: > On Apr 17, 5:13 pm, "Steve" <sjbur...@comcast.net> wrote: > > > > > "Joerg" <notthisjoerg...@removethispacbell.net> wrote in message > > >news:U5MNj.6956$GE1.6193@nlpi061.nbdc.sbc.com... > > > > qrk wrote: > > >> On Thu, 17 Apr 2008 09:43:09 -0700 (PDT), Dave <dhsch...@gmail.com> > > >> wrote: > > > >>> Does anybody out there have a good methodology for determining your > > >>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? > > >>> The brute force method is fairly maddening. I'd be curious to hear if > > >>> anybody has any 'tricks of the trade' here. > > > >>> Also, just out of curiosity, how many of you do your own PCB layout, > > >>> versus farming it out? It would certainly save us a lot of money to > > >>> buy the tools and do it ourselves, but it seems like laying out a > > >>> board out well requires quite a bit of experience, especially a 6-8 > > >>> layer board with high pin count FPGA's. > > > >>> We're just setting up a hardware shop here, and although I've been > > >>> doing FPGA and board schematics design for a while, it's always been > > >>> at a larger company with resources to farm the layout out, and we > > >>> never did anything high-speed to really worry about the board layout > > >>> too much. Thanks in advance for your opinions. > > > >>> Dave > > > >> Sure wish there was a slick way of doing FPGA pinouts. I usually use > > >> graph paper and figure out the FPGA pinout to other parts to minimize > > >> routing snarls. > > > >> I do pcb layouts on my own and other folks designs. Our boards have > > >> high-speed routing, switching power supplies, and high-gain analog > > >> stuff; sometimes all on the same board. Unless the service bureau has > > >> someone who understands how to lay out such circuitry and place > > >> sensitive analog stuff near digital junk, it is more trouble to farm > > >> out than do it yourself if you want the board to work on the first > > >> cut. > > > > Or find a good layouter and develop a long-term business relationship. My > > > layouter knows just from looking at a schematic which areas are critical. > > > He's a lot older than I am and that is probably one of the reasons why his > > > stuff works without much assistance from me. Nothing can replace a few > > > decades of experience. > > > >> Doing your own layout will take a lot of learning to master the PCB > > >> layout program and what your board vendor can handle. It will take 5 > > >> to 10 complicated boards to become mildly proficient at layout. I > > >> don't know about saving cost. Your time may be better spent doing > > >> other activities rather than learning about layout and doing the > > >> layouts. ... > > > > Yep, that's why I usually do not do my own layouts. Occassionally I route > > > a small portion of a circuit and send that to my layouter. No DRC or > > > anything, just to show him how I'd like it done. > > > >> ... The upside to doing your own layout - you control the whole > > >> design from start to finish. If you have a challenging layout, you'll > > >> have a much higher probability of having a working board on the first > > >> try which has hidden savings (getting to market earlier <- less > > >> troubleshooting + less respins). > > > >> --- > > >> Mark > > > > -- > > > Regards, Joerg > > > >http://www.analogconsultants.com/ > > > > "gmail" domain blocked because of excessive spam. > > > Use another domain or send PM. > > > I agree with Joerg. Good high speed or mixed signal PCB layout is a career > > choice, and we electrical engineers already chose our career. A good layout > > requires someone who understands not just the software package, but the > > details of how the manufacturing operation is going to proceed, what the > > limits of the processes are, what the assembly operations require of the > > board, and is anal about things like footprint libraries and solder mask > > clearances and a thousand other details that I'm only partially aware of. > > The more complex your design, the more critical these things become. > > > I have two good local outfits for farming out boards. For complex stuff, > > they know I'll come to their place and sit next to the designer for a good > > bit of the initial placement. While we are doing placement, we are also > > discussing critical nets, routing paths, layer usage, etc. That gives us > > direct face to face communication and avoids spending lots of time trying to > > write/draw everything in gory detail (which gets ignored or misunderstood a > > lot of the time). That investment pays big dividends in schedule and board > > performance. > > > Don't be fooled by the relatively low cost of the software. That's not where > > the big costs are. > > > I once laid off my entire PCB layout department and sent all the work > > outside, because although my employees all knew how to use the software, > > none of them could tell me what their completion date would be, or how many > > hours it would take, and they certainly weren't interested in meeting > > schedules. The outside sources would commit to a cost and a delivery date. > > And we already knew they could meet our performance objectives. Fixed price > > contracts are great motivators. Missing an engineering test window, or > > slipping a production schedule because of a layout delay can be enormously > > expensive. > > > Of course, if I had let my engineers do their own layouts, the motivation > > would have been present, but the technical proficiency would not. How > > proficient can anyone become if they only do layout a few times a year? > > Also, on many projects engineers use the layout period for other important > > things like documentation, test procedures, writing test code, etc. Doing > > your own layout serializes these tasks and will stretch your schedule. > > > So my advice is to keep doing what you have been doing. Its far more likely > > that its the cheapest approach, even though you occasionally have to write a > > big check. > > > Steve > > I tend to agree with the 'farm-it-out' crowd. Unfortunately, my > current employer doesn't want to work with my previous layout people, > so I've been trying to search for a new partner. I've found plenty of > board fab and assembly places, but not so much on the layout. It made > me think that the rest of the world did their own layout. The opinions > look pretty split from the replies here, maybe it comes down to how > many times you do a layout each year, and how much you enjoy that sort > of work. I definitely think it's something you have to do fairly often > to keep your chops up. > > Andy, I'd also like to hear more about your pin-swap FPGA design flow > - what tools do that? Also curious about any timing issues that have > been caught after the pin-swap. In Altium Designer I use the incredibly useful "subnet jumper" feature for BGA's. The procedure goes something like this: 1) Fan out all the required FPGA pins first (automatically or manually) to just outside the chip boundry. (leave several diagonal entry paths for core and other power flood fills to get in) 2) Fully route all non-pin-swappable pins and other critical lines. 3) Ensure any other parts placements are near any required FPGA pins or block features you think you might need. 4) Route every track just short of the fanout tracks 5) Hit the "add subnet jumper" feature and it finishes the tracks and does all the pin swaps for you and updates the schematic. Probably needs a picture or two to explain it best though... The great part about subnet jumpers is if there are timing or other problems you can just remove the subnet jumpers and add/edit tracks and pins as needed and then replace the subnet jumpers. Only takes a minute or two. Dave. |
| 18 Apr 2008 08:31:05 |
| Joerg |
| Re: Survey: FPGA PCB layout |
John Larkin wrote: > On Thu, 17 Apr 2008 09:43:09 -0700 (PDT), Dave <dhschetz@gmail.com> > wrote: > >> Does anybody out there have a good methodology for determining your >> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >> The brute force method is fairly maddening. I'd be curious to hear if >> anybody has any 'tricks of the trade' here. > > What's the brute force method? We preassign most fpga pins for clean, > no-crossover routing to other chips. We discuss the general issues, > especially placement, with our pcb layout guy and he actually decides > which pins go where. Then he back-annotates the schematic and gives us > a file we can use to create the fpga pin constraints file. Sometimes > bank issues complicate the process, but it works pretty well. > >> Also, just out of curiosity, how many of you do your own PCB layout, >> versus farming it out? It would certainly save us a lot of money to >> buy the tools and do it ourselves, but it seems like laying out a >> board out well requires quite a bit of experience, especially a 6-8 >> layer board with high pin count FPGA's. > > We'd never farm it out. We do critical mixed-signal stuff, and need to > be near our layout guy constantly. He puts up a version on our server > daily at least, and we keep an eye on progress. And we have a lot of > mini-meetings to change the rules as needed. Besides, we have evolved > some styles (and libraries!) that we couldn't very well transfer to a > service bureau. PCB layout is too important to farm out. > I always farm out the layout. At the most I do a mock layout of, say, a hotrod RF amp area and send it to the layouter. During layout Gerbers go back and forth all the time, sometimes in 15min intervals. Once my layouter had to be in Vermont during the job, no problem. Crunch time, he worked into the night, I had a laptop in the living room and whenever it beeped I'd go into the office, check the Gerbers and reply. Also really nice was a company overseas. I only had to check some critical areas during layout (which was done over there). They used a subversion system so a scattered team could cooperate without accidentally stepping on each others files. It was almost as if their server was here in the basement. >> We're just setting up a hardware shop here, and although I've been >> doing FPGA and board schematics design for a while, it's always been >> at a larger company with resources to farm the layout out, and we >> never did anything high-speed to really worry about the board layout >> too much. Thanks in advance for your opinions. > > > For really critical stuff, sometimes I'll take over and route that > part of the board myself. It's just too hard to communicate exactly > what I want. > Yes, for really hot stuff it's good to sit next to each other. In the past I'd driver over there and me, the layouter and his cat would do the tough parts of the layout together. Unfortunately his cat has passed away by now. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. |
| 18 Apr 2008 09:50:39 |
| Joel Koltner |
| Re: Survey: FPGA PCB layout |
"Joerg" <notthisjoergsch@removethispacbell.net > wrote in message news:0SSNj.2092$7Z2.69@newssvr12.news.prodigy.net... > Errr, well, those sure sound like ivory tower statements. For some reason > all the phenolic I ever used has never smelled. Maybe you're missing those receptors in your nose? :-) I've found that phenolic has a much stronger smell than FR-4... not necessarily all that "malodorous" vs. any other common board materials, but definitely a lot more noticeable. > Sometimes I wish that professors had more nose-to-the-grindstone industry > work under the belt. I mean real design work where cost is a big factor. > Otherwise they are going to tell students they should use Rogers for just > about everything ... Yep, that is a problem. Have you been to something like IEEE's MTT-S recently? It really is a different world, and unfortunately the same part of our culture that now says you need a BSEE to be an oscilloscope salesman is, I think, what has made it much more difficult for working engineers to enter academia. Becoming a EE professor is now seen as a career in and of itself, rather to the preclusion of of being a "practicing" engineer where you have significant cost constraints. ---Joel |
| 18 Apr 2008 10:05:14 |
| Joel Koltner |
| Re: Survey: FPGA PCB layout |
"David L. Jones" <altzone@gmail.com > wrote in message news:b60473de-efdf-458a-aae3-ebc5ea85b9e6@a1g2000hsb.googlegroups.com... > 5) Hit the "add subnet jumper" feature and it finishes the tracks and > does all the pin swaps for you and updates the schematic. Sounds like a really nice feature, David -- thanks for the tip. |
| 18 Apr 2008 17:10:22 |
| Joerg |
| Re: Survey: FPGA PCB layout |
Joel Koltner wrote: > "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message > news:0SSNj.2092$7Z2.69@newssvr12.news.prodigy.net... >> Errr, well, those sure sound like ivory tower statements. For some reason >> all the phenolic I ever used has never smelled. > > Maybe you're missing those receptors in your nose? :-) I've found that > phenolic has a much stronger smell than FR-4... not necessarily all that > "malodorous" vs. any other common board materials, but definitely a lot more > noticeable. > Possibly :-) Just went over to the lab and took a sniff. The really old dark versions might have a wee scent but the newer more light boards don't. The shepherd looked at me quite puzzled when I sniffed the boards. So she took a sniff as well but walked away upon dicovering that it ain't edible. If there were a stench she'd have sneezed. >> Sometimes I wish that professors had more nose-to-the-grindstone industry >> work under the belt. I mean real design work where cost is a big factor. >> Otherwise they are going to tell students they should use Rogers for just >> about everything ... > > Yep, that is a problem. Have you been to something like IEEE's MTT-S > recently? It really is a different world, and unfortunately the same part of > our culture that now says you need a BSEE to be an oscilloscope salesman is, I > think, what has made it much more difficult for working engineers to enter > academia. Becoming a EE professor is now seen as a career in and of itself, > rather to the preclusion of of being a "practicing" engineer where you have > significant cost constraints. > IEEE also needs step onto the real world of engineering, and soon. Else member retention will become a problem. I'd be interested in teaching once I retire but the bureaucratic hurdles are so high that it might have to be in a more private setting, without academic institutions, colleges or schools involved. I am not going to spend thousands on a teaching credential just to appease some bureaucrat. And the students must be motivated, otherwise I won't do it. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. |
| 18 Apr 2008 14:05:24 |
| Chuck Harris |
| Re: Survey: FPGA PCB layout |
Joerg wrote: > > I'd be interested in teaching once I retire but the bureaucratic hurdles > are so high that it might have to be in a more private setting, without > academic institutions, colleges or schools involved. I am not going to > spend thousands on a teaching credential just to appease some > bureaucrat. And the students must be motivated, otherwise I won't do it. Teaching doesn't require much in the way of credentials for university level. Getting on the tenure track is an entirely different matter. If you want to teach, head off to see the dean of your local university/community college, and ask what they need. Not much money, but it still can be a very satisfying experience. -Chuck |
| 18 Apr 2008 18:10:11 |
| qrk |
| Re: Survey: FPGA PCB layout |
On Thu, 17 Apr 2008 17:52:38 -0700, "Joel Koltner" <zapwireDASHgroups@yahoo.com > wrote: >"Joerg" <notthisjoergsch@removethispacbell.net> wrote in message >news:ZjRNj.9697$2g1.9469@nlpi068.nbdc.sbc.com... >> Not anymore. Part of my daily bread is earned salvaging designs where >> someone thought "Oh, it's just slow stuff". But it ain't grampa's old SN7400 >> anymore, today's logic chips are fast. > >OK, ok, good point. Doesn't someone now have a logic family that's purposely >been slowed down due to this "problem?" > [snippage] You can control edge rates (drive current) on FPGAs, at least the Xilinx families we use. Amazing how simple you can make a DDR2 memory interface to a FPGA with a little thought. We get by with no terminations with beautiful looking signals. That saves a lot of power and board area. --- Mark |
| 18 Apr 2008 11:11:43 |
| Joerg |
| Re: Survey: FPGA PCB layout |
Chuck Harris wrote: > Joerg wrote: > >> >> I'd be interested in teaching once I retire but the bureaucratic >> hurdles are so high that it might have to be in a more private >> setting, without academic institutions, colleges or schools involved. >> I am not going to spend thousands on a teaching credential just to >> appease some bureaucrat. And the students must be motivated, otherwise >> I won't do it. > > Teaching doesn't require much in the way of credentials for university > level. > Getting on the tenure track is an entirely different matter. > There shouldn't be any tenure in the first place. There is a reason why the tenure concept does not exist in industry. Just my humble opinion. > If you want to teach, head off to see the dean of your local > university/community > college, and ask what they need. Not much money, but it still can be a > very > satisfying experience. > Some day I will, when I throttle back design work and money (hopefully) isn't a big issue. It doesn't have to be any ritzy school as long as the audience is motivated and the school isn't a huge driving distance away. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. |
| 18 Apr 2008 11:51:37 |
| Joel Koltner |
| Re: Survey: FPGA PCB layout |
"Joerg" <notthisjoergsch@removethispacbell.net > wrote in message news:Zv5Oj.4677$iK6.2580@nlpi069.nbdc.sbc.com... > There shouldn't be any tenure in the first place. There is a reason why the > tenure concept does not exist in industry. Just my humble opinion. Doesn't tenure just mean that you have to screw up particularly badly to get fired? And that even after you officially quit teaching/researching you're generally still allowed to come and play in the lab and perhaps have an office? Or is there more to it than that? I was asked to write a letter of recommendation for a professor I had to turn him from an assistant professor into a full-fledged (and perhaps tenure track?) professor. He's a good teacher so I was happy to do it, but I found it a little odd that the professor in charge of this whole process said, "If you don't feel you can write a letter that presents [this guy] in a positive light, it's OK -- let me know and we'll find someone else." Hmmm....! > Some day I will, when I throttle back design work and money (hopefully) > isn't a big issue. It doesn't have to be any ritzy school as long as the > audience is motivated and the school isn't a huge driving distance away. These days "distance learning" is becoming quite popular. You could probably host your own classes on more advanced/specialized topics (where they might not be enough people interested to get an actual physical class together in a smaller town), set it up so that everyone gets audio & video and remote students can send back audio (for questions/discussion), charge tuition to cover the conference server feels, your costs and compensation, etc. and be quite successful. Doug Smith (http://www.emcesd.com/)appears to have done pretty well with his approach of giving away a *significant* amount of useful information for free and then having a subscription service for those who want even more. ---Joel |
| 18 Apr 2008 12:28:29 |
| Joerg |
| Re: Survey: FPGA PCB layout |
Joel Koltner wrote: > "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message > news:Zv5Oj.4677$iK6.2580@nlpi069.nbdc.sbc.com... >> There shouldn't be any tenure in the first place. There is a reason why the >> tenure concept does not exist in industry. Just my humble opinion. > > Doesn't tenure just mean that you have to screw up particularly badly to get > fired? And that even after you officially quit teaching/researching you're > generally still allowed to come and play in the lab and perhaps have an > office? Or is there more to it than that? > Plus probably a nice retirement benefit. > I was asked to write a letter of recommendation for a professor I had to turn > him from an assistant professor into a full-fledged (and perhaps tenure > track?) professor. He's a good teacher so I was happy to do it, but I found > it a little odd that the professor in charge of this whole process said, "If > you don't feel you can write a letter that presents [this guy] in a positive > light, it's OK -- let me know and we'll find someone else." Hmmm....! > That is strange. Normally they should have known this guy inside out before even offering tenure if that's what his new position entails. >> Some day I will, when I throttle back design work and money (hopefully) >> isn't a big issue. It doesn't have to be any ritzy school as long as the >> audience is motivated and the school isn't a huge driving distance away. > > These days "distance learning" is becoming quite popular. You could probably > host your own classes on more advanced/specialized topics (where they might > not be enough people interested to get an actual physical class together in a > smaller town), set it up so that everyone gets audio & video and remote > students can send back audio (for questions/discussion), charge tuition to > cover the conference server feels, your costs and compensation, etc. and be > quite successful. > True, but I am a believer in face to face sessions when it comes to explaining EE matters. You can't beat the hands-on training in front of a big scope or analyzer. "Sir, I can't get that dang thang to trigger!" > Doug Smith (http://www.emcesd.com/)appears to have done pretty well with his > approach of giving away a *significant* amount of useful information for free > and then having a subscription service for those who want even more. > Yes, his site is indeed excellent. I am surprised IEEE lets him publish his papers. When I wrote papers for IEEE transactions there was a pretty clear statement that you pretty much surrender copyright to them. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. |
| 18 Apr 2008 12:57:56 |
| Joel Koltner |
| Re: Survey: FPGA PCB layout |
"Joerg" <notthisjoergsch@removethispacbell.net > wrote in message news:KD6Oj.9778$2g1.2542@nlpi068.nbdc.sbc.com... > That is strange. Normally they should have known this guy inside out before > even offering tenure if that's what his new position entails. I believe they did know him inside and out, were happy with his performance, and that's why it happened: They had already decided they were going to offer him the promotion, but some standard procedure required getting a student evaluation as well... so they had to find someone who was willing to write up a positive one. I just think it's strange that they bother getting a student evaluation when their minds are already made up... since it then puts them in the rather awkward position of having to say, "Please write us a good evaluation, or if you don't feel you can, that's OK, we'll find someone else..." Weird. Perhaps they'd do better to ask a handful of students to write up objective evaluations without the pressure of "...but, um, it has to be positive?" -- and then culling any that were negative? :-) I suppose they're stuck in a way... being tied to the government (they're a land-grant university) means they have to follow lots of procedures that regular businesses don't. Regarding the nice retirement packages... my understanding was that state workers ended up with rather cushy retirement packages in exchange for having to accept noticeably below-average salaries (relative to private industry) during their working years. In Oreogn we have the PERS (Public Employee Retirement System) which used to work this way, but the "cushy" benefits were signifcantly reduced via the ballot box when some interested parties pointed out how much better PERS was than what those folks in private industry get. Hence you now have a system where public employee pay still isn't competitive with private industry and now the retirement isn't either! This was a common topic of complaint by the professors (that you'd get to know well enough) when I was in grad school; a significant number left for private industry during that time, and I certainly coudn't blame them. That being said, I don't know enough to evaluate whether or not public jobs are still attractive when you look at the total package -- some people would argue they are and that PERS benefit reductions were just "corrections" to a system that had become too "generous" in its compensation. ---Joel |
| 18 Apr 2008 20:22:49 |
| Joerg |
| Re: Survey: FPGA PCB layout |
Joel Koltner wrote: > "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message > news:KD6Oj.9778$2g1.2542@nlpi068.nbdc.sbc.com... >> That is strange. Normally they should have known this guy inside out before >> even offering tenure if that's what his new position entails. > > I believe they did know him inside and out, were happy with his performance, > and that's why it happened: They had already decided they were going to offer > him the promotion, but some standard procedure required getting a student > evaluation as well... so they had to find someone who was willing to write up > a positive one. I just think it's strange that they bother getting a student > evaluation when their minds are already made up... since it then puts them in > the rather awkward position of having to say, "Please write us a good > evaluation, or if you don't feel you can, that's OK, we'll find someone > else..." Weird. > > Perhaps they'd do better to ask a handful of students to write up objective > evaluations without the pressure of "...but, um, it has to be positive?" -- > and then culling any that were negative? :-) I suppose they're stuck in a > way... being tied to the government (they're a land-grant university) means > they have to follow lots of procedures that regular businesses don't. > > Regarding the nice retirement packages... my understanding was that state > workers ended up with rather cushy retirement packages in exchange for having > to accept noticeably below-average salaries (relative to private industry) > during their working years. In Oreogn we have the PERS (Public Employee > Retirement System) which used to work this way, but the "cushy" benefits were > signifcantly reduced via the ballot box when some interested parties pointed > out how much better PERS was than what those folks in private industry get. > Hence you now have a system where public employee pay still isn't competitive > with private industry and now the retirement isn't either! This was a common > topic of complaint by the professors (that you'd get to know well enough) when > I was in grad school; a significant number left for private industry during > that time, and I certainly coudn't blame them. > > That being said, I don't know enough to evaluate whether or not public jobs > are still attractive when you look at the total package -- some people would > argue they are and that PERS benefit reductions were just "corrections" to a > system that had become too "generous" in its compensation. > All I know from here (CA) is that their benefits are mind-boggling. Paid sick leave, fat disability payments where lots of people tried and succeeded to be declared "disabled", cradle-to-grave medical with hardly any co-pay. The latter alone will saddle our communities with previously unheard of debt. Oh, and then lots of jobs have the retirement benefit tied to the last work year. So, folks have themselves transferred into high-cost areas such as the Bay Area for 13 months or so, then move back. That ratchets their monthly checks up substantially, until their dying day. That ain't right. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. |
| 18 Apr 2008 13:42:54 |
| Joel Koltner |
| Re: Survey: FPGA PCB layout |
"Joerg" <notthisjoergsch@removethispacbell.net > wrote in message news:tq7Oj.1556$FF6.588@newssvr29.news.prodigy.net... > All I know from here (CA) is that their benefits are mind-boggling... Well, it's entirely reasonable to have retirement benefits for public employees be comparable to what private companies offer... I just hope that public employee salaries will then become comparable as well (which implies a pay raise), since otherwise I don't see how the gov't. expects they'll get comparable quality out of their workers. One problem with the government seems to be that they don't expect their employees to be agile over time. See this article: http://www.gcn.com/print/24_30/37174-1.html-- Someone the government ends up with a bunch of 70 year old programmers and therefore has to hire IBM to build them the modernized e-filing systems? Surely there must be some new hires in the past, say, 40 years who could have been working on this and hence, on average, would only be middle-aged today!? > Oh, and then lots of jobs have the retirement benefit tied to the last work > year. I expect that was implemented to help people who were *forced* to move? It seems like it needs reworking to differentiate between cases where the government wants to move you vs. you just voluntarily wanting to do so. ---Joel |
| 18 Apr 2008 21:07:25 |
| Nico Coesel |
| Re: Survey: FPGA PCB layout |
Dave <dhschetz@gmail.com > wrote: >Does anybody out there have a good methodology for determining your >optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >The brute force method is fairly maddening. I'd be curious to hear if >anybody has any 'tricks of the trade' here. I start thinking about how the PCB should be routed the minute I start to draw a schematic. I always draw components with their actual pin-outs. This helps to group pins together and it helps to troubleshoot the circuit when the prototype is on your bench (no need to lookup the pinouts because they are in your diagram). >Also, just out of curiosity, how many of you do your own PCB layout, >versus farming it out? It would certainly save us a lot of money to >buy the tools and do it ourselves, but it seems like laying out a Whether you should do PCB layout by yourself or hire someone to do it for you depends on if you have the time and talent to design a PCB. After all at high frequencies and / or large currents a PCB becomes a component of your circuit. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.) |
| 18 Apr 2008 16:23:18 |
| Hal Murray |
| Re: Survey: FPGA PCB layout |
> I always draw components with their actual >pin-outs. What does that mean? -- These are my opinions, not necessarily my employer's. I hate spam. |
| 18 Apr 2008 14:39:02 |
| Joel Koltner |
| Re: Survey: FPGA PCB layout |
"Hal Murray" <hal-usenet@ip-64-139-1-69.sjc.megapath.net > wrote in message news:JdudnXIVmePbjJTVnZ2dnUVZ_vfinZ2d@megapath.net... >> I always draw components with their actual >>pin-outs. > What does that mean? I suspect he means that the schematic symbol he draws have the pins arranged with the same placement as that which occurs on the physical device. I've drawn some symbols like this at times, as it works OK for small devices, but of course has problems as soon as someone hits the "mirror" button on your symbol... and becomes intractable for devices with hundreds or even thousands of pins. You sometimes see magazines doing this in beginning electronics articles where they'll have a bunch of logic gates or similar drawn nicely within the DIP rectangle it comes in on top of a solderless breadboard or something so it's crystal clear how the circuit should be wired up. |
| 19 Apr 2008 08:41:37 |
| Nico Coesel |
| Re: Survey: FPGA PCB layout |
"Joel Koltner" <zapwireDASHgroups@yahoo.com > wrote: >"Hal Murray" <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote in message >news:JdudnXIVmePbjJTVnZ2dnUVZ_vfinZ2d@megapath.net... >>> I always draw components with their actual >>>pin-outs. >> What does that mean? > >I suspect he means that the schematic symbol he draws have the pins arranged >with the same placement as that which occurs on the physical device. > >I've drawn some symbols like this at times, as it works OK for small devices, >but of course has problems as soon as someone hits the "mirror" button on your >symbol... and becomes intractable for devices with hundreds or even thousands >of pins. Mirroring is not allowed ofcourse :-) And yes, it won't work for BGA packages. The largest common QFP device is approx 200 pins which is still workable. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.) |
| 19 Apr 2008 13:39:10 |
| Joerg |
| Re: Survey: FPGA PCB layout |
Joel Koltner wrote: > "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message > news:tq7Oj.1556$FF6.588@newssvr29.news.prodigy.net... >> All I know from here (CA) is that their benefits are mind-boggling... > > Well, it's entirely reasonable to have retirement benefits for public > employees be comparable to what private companies offer... I just hope that > public employee salaries will then become comparable as well (which implies a > pay raise), since otherwise I don't see how the gov't. expects they'll get > comparable quality out of their workers. > Private companies generally offer zilch in retirement benefits. Those days are long gone. > One problem with the government seems to be that they don't expect their > employees to be agile over time. See this article: > http://www.gcn.com/print/24_30/37174-1.html-- Someone the government ends up > with a bunch of 70 year old programmers and therefore has to hire IBM to build > them the modernized e-filing systems? Surely there must be some new hires in > the past, say, 40 years who could have been working on this and hence, on > average, would only be middle-aged today!? > A 70 year old programmer can be better than a 40 year old. At least that's my impression when I see all the "modern" bloatware ;-) >> Oh, and then lots of jobs have the retirement benefit tied to the last work >> year. > > I expect that was implemented to help people who were *forced* to move? > > It seems like it needs reworking to differentiate between cases where the > government wants to move you vs. you just voluntarily wanting to do so. > Or you just have to have the right connections to make that happen ... Anyhow, why should retirement checks be based on the last year of service? IMHO that's wrong. For everyone else it sure doesn't work that way. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. |
| 19 Apr 2008 14:17:44 |
| Joerg |
| Re: Survey: FPGA PCB layout |
Nico Coesel wrote: > Dave <dhschetz@gmail.com> wrote: > >> Does anybody out there have a good methodology for determining your >> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >> The brute force method is fairly maddening. I'd be curious to hear if >> anybody has any 'tricks of the trade' here. > > I start thinking about how the PCB should be routed the minute I start > to draw a schematic. I always draw components with their actual > pin-outs. This helps to group pins together and it helps to > troubleshoot the circuit when the prototype is on your bench (no need > to lookup the pinouts because they are in your diagram). > For quad opamps like the LM324 as well? That can make a schematic harder to read and will also cause a nightmare if the layouter wants to swap amp A with amp C and stuff like that. [...] -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. |
| 19 Apr 2008 20:47:57 |
| krw |
| Re: Survey: FPGA PCB layout |
In article <PLsOj.7522$GE1.332@nlpi061.nbdc.sbc.com >, notthisjoergsch@removethispacbell.net says... > Joel Koltner wrote: > > "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message > > news:tq7Oj.1556$FF6.588@newssvr29.news.prodigy.net... > >> All I know from here (CA) is that their benefits are mind-boggling... > > > > Well, it's entirely reasonable to have retirement benefits for public > > employees be comparable to what private companies offer... I just hope that > > public employee salaries will then become comparable as well (which implies a > > pay raise), since otherwise I don't see how the gov't. expects they'll get > > comparable quality out of their workers. > > > > Private companies generally offer zilch in retirement benefits. Those > days are long gone. I don't know about "gone". The age of the "defined benefit" is pretty much gone in private industry but several still have "defined contribution" plans. Now, 401Ks make up for a lot of what's been lost and are portable. > > One problem with the government seems to be that they don't expect their > > employees to be agile over time. See this article: > > http://www.gcn.com/print/24_30/37174-1.html-- Someone the government ends up > > with a bunch of 70 year old programmers and therefore has to hire IBM to build > > them the modernized e-filing systems? Surely there must be some new hires in > > the past, say, 40 years who could have been working on this and hence, on > > average, would only be middle-aged today!? > > > > A 70 year old programmer can be better than a 40 year old. At least > that's my impression when I see all the "modern" bloatware ;-) Maybe. There are better things to do at 70, though. ;-) > > >> Oh, and then lots of jobs have the retirement benefit tied to the last work > >> year. > > > > I expect that was implemented to help people who were *forced* to move? > > > > It seems like it needs reworking to differentiate between cases where the > > government wants to move you vs. you just voluntarily wanting to do so. > > > > Or you just have to have the right connections to make that happen ... > > Anyhow, why should retirement checks be based on the last year of > service? IMHO that's wrong. For everyone else it sure doesn't work that way. The last years' is indicative of the final salary. Most "defined benefit" plans do take the last year, or last couple of years into account. What most private pensions *don't* do, that public plans do is include overtime in the formula. It's not hard to double one's income for a couple of years. There is no way the tax payer should pay that forever. -- Keith |
| 20 Apr 2008 00:54:44 |
| Joerg |
| Re: Survey: FPGA PCB layout |
krw wrote: > In article <PLsOj.7522$GE1.332@nlpi061.nbdc.sbc.com>, > notthisjoergsch@removethispacbell.net says... >> Joel Koltner wrote: >>> "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message >>> news:tq7Oj.1556$FF6.588@newssvr29.news.prodigy.net... >>>> All I know from here (CA) is that their benefits are mind-boggling... >>> Well, it's entirely reasonable to have retirement benefits for public >>> employees be comparable to what private companies offer... I just hope that >>> public employee salaries will then become comparable as well (which implies a >>> pay raise), since otherwise I don't see how the gov't. expects they'll get >>> comparable quality out of their workers. >>> >> Private companies generally offer zilch in retirement benefits. Those >> days are long gone. > > I don't know about "gone". The age of the "defined benefit" is > pretty much gone in private industry but several still have "defined > contribution" plans. Now, 401Ks make up for a lot of what's been > lost and are portable. > Sure, but 401(k) is generally funded by the employee. Occasionally the company throws in a little extra but that is mostly a mere drop in the bucket in contrast to the lavish pension plans that cover many state workers. >>> One problem with the government seems to be that they don't expect their >>> employees to be agile over time. See this article: >>> http://www.gcn.com/print/24_30/37174-1.html-- Someone the government ends up >>> with a bunch of 70 year old programmers and therefore has to hire IBM to build >>> them the modernized e-filing systems? Surely there must be some new hires in >>> the past, say, 40 years who could have been working on this and hence, on >>> average, would only be middle-aged today!? >>> >> A 70 year old programmer can be better than a 40 year old. At least >> that's my impression when I see all the "modern" bloatware ;-) > > Maybe. There are better things to do at 70, though. ;-) Yes, definitely. OTOH completely quitting a career has brought many fine engineers into the grave within less than a year. My father who worked as a data processing engineer continued as a consultant and gradually tapered it off. He said that there was a rash of unexpected deaths of otherwise quite healthy colleagues right after retirement, and it was among the group of engineers who shut their careers down more or less overnight after the first retirement check arrived. >>>> Oh, and then lots of jobs have the retirement benefit tied to the last work >>>> year. >>> I expect that was implemented to help people who were *forced* to move? >>> >>> It seems like it needs reworking to differentiate between cases where the >>> government wants to move you vs. you just voluntarily wanting to do so. >>> >> Or you just have to have the right connections to make that happen ... >> >> Anyhow, why should retirement checks be based on the last year of >> service? IMHO that's wrong. For everyone else it sure doesn't work that way. > > The last years' is indicative of the final salary. Most "defined > benefit" plans do take the last year, or last couple of years into > account. What most private pensions *don't* do, that public plans > do is include overtime in the formula. It's not hard to double > one's income for a couple of years. There is no way the tax payer > should pay that forever. > But it's happening. And we are all paying for that. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. |
| 19 Apr 2008 22:34:30 |
| krw |
| Re: Survey: FPGA PCB layout |
In article <ovwOj.2084$pS4.1733@newssvr13.news.prodigy.net >, notthisjoergsch@removethispacbell.net says... > krw wrote: > > In article <PLsOj.7522$GE1.332@nlpi061.nbdc.sbc.com>, > > notthisjoergsch@removethispacbell.net says... > >> Joel Koltner wrote: > >>> "Joerg" <notthisjoergsch@removethispacbell.net> wrote in message > >>> news:tq7Oj.1556$FF6.588@newssvr29.news.prodigy.net... > >>>> All I know from here (CA) is that their benefits are mind-boggling... > >>> Well, it's entirely reasonable to have retirement benefits for public > >>> employees be comparable to what private companies offer... I just hope that > >>> public employee salaries will then become comparable as well (which implies a > >>> pay raise), since otherwise I don't see how the gov't. expects they'll get > >>> comparable quality out of their workers. > >>> > >> Private companies generally offer zilch in retirement benefits. Those > >> days are long gone. > > > > I don't know about "gone". The age of the "defined benefit" is > > pretty much gone in private industry but several still have "defined > > contribution" plans. Now, 401Ks make up for a lot of what's been > > lost and are portable. > > > > Sure, but 401(k) is generally funded by the employee. Occasionally the > company throws in a little extra but that is mostly a mere drop in the > bucket in contrast to the lavish pension plans that cover many state > workers. It's quite normal for a company to add significantly to the 401K, sometimes with strings attached, sometimes without. My PPOE had a fairly decent 401K (in addition to pension plans for everyone joining before '06, or so). They matched 1:1 up to 6% of salary (plus bonusus) and had no management fees for the normal funds. I understand it's gotten better since they've dropped the pension plans for the newbs. > >>> One problem with the government seems to be that they don't expect their > >>> employees to be agile over time. See this article: > >>> http://www.gcn.com/print/24_30/37174-1.html-- Someone the government ends up > >>> with a bunch of 70 year old programmers and therefore has to hire IBM to build > >>> them the modernized e-filing systems? Surely there must be some new hires in > >>> the past, say, 40 years who could have been working on this and hence, on > >>> average, would only be middle-aged today!? > >>> > >> A 70 year old programmer can be better than a 40 year old. At least > >> that's my impression when I see all the "modern" bloatware ;-) > > > > Maybe. There are better things to do at 70, though. ;-) > > > Yes, definitely. OTOH completely quitting a career has brought many fine > engineers into the grave within less than a year. My father who worked > as a data processing engineer continued as a consultant and gradually > tapered it off. He said that there was a rash of unexpected deaths of > otherwise quite healthy colleagues right after retirement, and it was > among the group of engineers who shut their careers down more or less > overnight after the first retirement check arrived. I got quite bored, once I wasn't allowed to make messes at home anymore. Good thing that only lasted a week or two. ;-) > > >>>> Oh, and then lots of jobs have the retirement benefit tied to the last work > >>>> year. > >>> I expect that was implemented to help people who were *forced* to move? > >>> > >>> It seems like it needs reworking to differentiate between cases where the > >>> government wants to move you vs. you just voluntarily wanting to do so. > >>> > >> Or you just have to have the right connections to make that happen ... > >> > >> Anyhow, why should retirement checks be based on the last year of > >> service? IMHO that's wrong. For everyone else it sure doesn't work that way. > > > > The last years' is indicative of the final salary. Most "defined > > benefit" plans do take the last year, or last couple of years into > > account. What most private pensions *don't* do, that public plans > > do is include overtime in the formula. It's not hard to double > > one's income for a couple of years. There is no way the tax payer > > should pay that forever. > > > > But it's happening. And we are all paying for that. Precisely. It's not going to get better. The government requires others to have fully funded retirement plans, but would have none of it for themselves. -- Keith |
| 20 Apr 2008 08:21:52 |
| Nico Coesel |
| Re: Survey: FPGA PCB layout |
Joerg <notthisjoergsch@removethispacbell.net > wrote: >Nico Coesel wrote: >> Dave <dhschetz@gmail.com> wrote: >> >>> Does anybody out there have a good methodology for determining your >>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >>> The brute force method is fairly maddening. I'd be curious to hear if >>> anybody has any 'tricks of the trade' here. >> >> I start thinking about how the PCB should be routed the minute I start >> to draw a schematic. I always draw components with their actual >> pin-outs. This helps to group pins together and it helps to >> troubleshoot the circuit when the prototype is on your bench (no need >> to lookup the pinouts because they are in your diagram). >> > >For quad opamps like the LM324 as well? No. Those (and simple logic) have very few pins. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.) |
| 20 Apr 2008 13:22:46 |
| Joerg |
| Re: Survey: FPGA PCB layout |
Nico Coesel wrote: > Joerg <notthisjoergsch@removethispacbell.net> wrote: > >> Nico Coesel wrote: >>> Dave <dhschetz@gmail.com> wrote: >>> >>>> Does anybody out there have a good methodology for determining your >>>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >>>> The brute force method is fairly maddening. I'd be curious to hear if >>>> anybody has any 'tricks of the trade' here. >>> I start thinking about how the PCB should be routed the minute I start >>> to draw a schematic. I always draw components with their actual >>> pin-outs. This helps to group pins together and it helps to >>> troubleshoot the circuit when the prototype is on your bench (no need >>> to lookup the pinouts because they are in your diagram). >>> >> For quad opamps like the LM324 as well? > > No. Those (and simple logic) have very few pins. > Ok, then you'd have to modify your statement "always" :-) Am I the nitpicker or what? -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. |
| 20 Apr 2008 13:47:18 |
| John Larkin |
| Re: Survey: FPGA PCB layout |
On Sat, 19 Apr 2008 14:17:44 -0700, Joerg <notthisjoergsch@removethispacbell.net > wrote: >Nico Coesel wrote: >> Dave <dhschetz@gmail.com> wrote: >> >>> Does anybody out there have a good methodology for determining your >>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >>> The brute force method is fairly maddening. I'd be curious to hear if >>> anybody has any 'tricks of the trade' here. >> >> I start thinking about how the PCB should be routed the minute I start >> to draw a schematic. I always draw components with their actual >> pin-outs. This helps to group pins together and it helps to >> troubleshoot the circuit when the prototype is on your bench (no need >> to lookup the pinouts because they are in your diagram). >> > >For quad opamps like the LM324 as well? That can make a schematic harder >to read and will also cause a nightmare if the layouter wants to swap >amp A with amp C and stuff like that. > >[...] A quad opamp doesn't have 1738 pins! John |
| 20 Apr 2008 14:13:21 |
| Joerg |
| Re: Survey: FPGA PCB layout |
John Larkin wrote: > On Sat, 19 Apr 2008 14:17:44 -0700, Joerg > <notthisjoergsch@removethispacbell.net> wrote: > >> Nico Coesel wrote: >>> Dave <dhschetz@gmail.com> wrote: >>> >>>> Does anybody out there have a good methodology for determining your >>>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >>>> The brute force method is fairly maddening. I'd be curious to hear if >>>> anybody has any 'tricks of the trade' here. >>> I start thinking about how the PCB should be routed the minute I start >>> to draw a schematic. I always draw components with their actual >>> pin-outs. This helps to group pins together and it helps to >>> troubleshoot the circuit when the prototype is on your bench (no need >>> to lookup the pinouts because they are in your diagram). >>> >> For quad opamps like the LM324 as well? That can make a schematic harder >> to read and will also cause a nightmare if the layouter wants to swap >> amp A with amp C and stuff like that. >> >> [...] > > A quad opamp doesn't have 1738 pins! > Well, yes, I was just wondering about whether Nico really always draws the physical package. Looks like he doesn't for smaller stuff. With 1738 pins you can only hope that the FPGA has enough routing resources. That used to be a major pain in the early 90's. Don't know about nowadays since other guys design the parts with the big FPGAs. And I am glad I don't have to deal with BGA, at least not with large ones ... -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. |
| 20 Apr 2008 17:33:16 |
| Michael A. Terrell |
| Re: Survey: FPGA PCB layout |
John Larkin wrote: > > A quad opamp doesn't have 1738 pins! That will only happen if Bloggs designs it. :( -- http://improve-usenet.org/index.html Use any search engine other than Google till they stop polluting USENET with porn and junk commercial SPAM If you have broadband, your ISP may have a NNTP news server included in your account: http://www.usenettools.net/ISP.htm |
| 20 Apr 2008 14:56:15 |
| John Larkin |
| Re: Survey: FPGA PCB layout |
On Sun, 20 Apr 2008 14:13:21 -0700, Joerg <notthisjoergsch@removethispacbell.net > wrote: >John Larkin wrote: >> On Sat, 19 Apr 2008 14:17:44 -0700, Joerg >> <notthisjoergsch@removethispacbell.net> wrote: >> >>> Nico Coesel wrote: >>>> Dave <dhschetz@gmail.com> wrote: >>>> >>>>> Does anybody out there have a good methodology for determining your >>>>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >>>>> The brute force method is fairly maddening. I'd be curious to hear if >>>>> anybody has any 'tricks of the trade' here. >>>> I start thinking about how the PCB should be routed the minute I start >>>> to draw a schematic. I always draw components with their actual >>>> pin-outs. This helps to group pins together and it helps to >>>> troubleshoot the circuit when the prototype is on your bench (no need >>>> to lookup the pinouts because they are in your diagram). >>>> >>> For quad opamps like the LM324 as well? That can make a schematic harder >>> to read and will also cause a nightmare if the layouter wants to swap >>> amp A with amp C and stuff like that. >>> >>> [...] >> >> A quad opamp doesn't have 1738 pins! >> > >Well, yes, I was just wondering about whether Nico really always draws >the physical package. Looks like he doesn't for smaller stuff. > >With 1738 pins you can only hope that the FPGA has enough routing >resources. That used to be a major pain in the early 90's. Don't know >about nowadays since other guys design the parts with the big FPGAs. And >I am glad I don't have to deal with BGA, at least not with large ones ... The biggest ones we use are Sparten 3's with 456 balls on 1 mm centers. We haven't had any routing problems so far, doing pretty complex stuff at 128 MHz clock rates. Our in-house BGA soldering yield, to date, is exactly 100%. BGAs seem to be a lot easier to solder reliably than fine-pitch leaded parts. Easier to inspect, too, since you can't inspect them at all. John |
| 20 Apr 2008 14:59:57 |
| John Larkin |
| Re: Survey: FPGA PCB layout |
On Sun, 20 Apr 2008 17:33:16 -0400, "Michael A. Terrell" <mike.terrell@earthlink.net > wrote: > >John Larkin wrote: >> >> A quad opamp doesn't have 1738 pins! > > > That will only happen if Bloggs designs it. :( Bloggs has several times stated that he doesn't design electronics. He hasn't stated what he actually does. John |
| 20 Apr 2008 18:10:04 |
| Michael A. Terrell |
| Re: Survey: FPGA PCB layout |
John Larkin wrote: > > On Sun, 20 Apr 2008 17:33:16 -0400, "Michael A. Terrell" > <mike.terrell@earthlink.net> wrote: > > > > >John Larkin wrote: > >> > >> A quad opamp doesn't have 1738 pins! > > > > > > That will only happen if Bloggs designs it. :( > > Bloggs has several times stated that he doesn't design electronics. He > hasn't stated what he actually does. He stated that he does absolutely nothing. It might be the only time he has ever told the truth. -- http://improve-usenet.org/index.html Use any search engine other than Google till they stop polluting USENET with porn and junk commercial SPAM If you have broadband, your ISP may have a NNTP news server included in your account: http://www.usenettools.net/ISP.htm |
| 20 Apr 2008 19:31:50 |
| krw |
| Re: Survey: FPGA PCB layout |
In article <TlOOj.2407$I55.1437@newssvr22.news.prodigy.net >, notthisjoergsch@removethispacbell.net says... > John Larkin wrote: > > On Sat, 19 Apr 2008 14:17:44 -0700, Joerg > > <notthisjoergsch@removethispacbell.net> wrote: > > > >> Nico Coesel wrote: > >>> Dave <dhschetz@gmail.com> wrote: > >>> > >>>> Does anybody out there have a good methodology for determining your > >>>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? > >>>> The brute force method is fairly maddening. I'd be curious to hear if > >>>> anybody has any 'tricks of the trade' here. > >>> I start thinking about how the PCB should be routed the minute I start > >>> to draw a schematic. I always draw components with their actual > >>> pin-outs. This helps to group pins together and it helps to > >>> troubleshoot the circuit when the prototype is on your bench (no need > >>> to lookup the pinouts because they are in your diagram). > >>> > >> For quad opamps like the LM324 as well? That can make a schematic harder > >> to read and will also cause a nightmare if the layouter wants to swap > >> amp A with amp C and stuff like that. > >> > >> [...] > > > > A quad opamp doesn't have 1738 pins! > > > > Well, yes, I was just wondering about whether Nico really always draws > the physical package. Looks like he doesn't for smaller stuff. > > With 1738 pins you can only hope that the FPGA has enough routing > resources. That used to be a major pain in the early 90's. Don't know > about nowadays since other guys design the parts with the big FPGAs. And I had a *lot* of routing problems with the SpartanXL series. I had lotsa logic left but if it would route it would take days. I didn't have any problems, at the time, with Virtex or Vertex-E. Now the Virtex-2s and 4s route in a small number of minutes with no errors. > I am glad I don't have to deal with BGA, at least not with large ones ... I don't deal with them either. That's the layouter's job. ;-) Actually, right now I just work on what goes into them (though I had to completely redesign a badly screwed up board in December, which we *still* don't have back). -- Keith |
| 20 Apr 2008 17:00:46 |
| Joerg |
| Re: Survey: FPGA PCB layout |
John Larkin wrote: > On Sun, 20 Apr 2008 14:13:21 -0700, Joerg > <notthisjoergsch@removethispacbell.net> wrote: > >> John Larkin wrote: >>> On Sat, 19 Apr 2008 14:17:44 -0700, Joerg >>> <notthisjoergsch@removethispacbell.net> wrote: >>> >>>> Nico Coesel wrote: >>>>> Dave <dhschetz@gmail.com> wrote: >>>>> >>>>>> Does anybody out there have a good methodology for determining your >>>>>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? >>>>>> The brute force method is fairly maddening. I'd be curious to hear if >>>>>> anybody has any 'tricks of the trade' here. >>>>> I start thinking about how the PCB should be routed the minute I start >>>>> to draw a schematic. I always draw components with their actual >>>>> pin-outs. This helps to group pins together and it helps to >>>>> troubleshoot the circuit when the prototype is on your bench (no need >>>>> to lookup the pinouts because they are in your diagram). >>>>> >>>> For quad opamps like the LM324 as well? That can make a schematic harder >>>> to read and will also cause a nightmare if the layouter wants to swap >>>> amp A with amp C and stuff like that. >>>> >>>> [...] >>> A quad opamp doesn't have 1738 pins! >>> >> Well, yes, I was just wondering about whether Nico really always draws >> the physical package. Looks like he doesn't for smaller stuff. >> >> With 1738 pins you can only hope that the FPGA has enough routing >> resources. That used to be a major pain in the early 90's. Don't know >> about nowadays since other guys design the parts with the big FPGAs. And >> I am glad I don't have to deal with BGA, at least not with large ones ... > > The biggest ones we use are Sparten 3's with 456 balls on 1 mm > centers. We haven't had any routing problems so far, doing pretty > complex stuff at 128 MHz clock rates. Our in-house BGA soldering > yield, to date, is exactly 100%. BGAs seem to be a lot easier to > solder reliably than fine-pitch leaded parts. Easier to inspect, too, > since you can't inspect them at all. > The latter is a concern in my field (medical). We need to be able to inspect. The other concern is involuntary board flexing. Most of my designs have to sustain under tortures such as freighter pilots ploughing through a storm in the Carribean in airplanes as old as a DC-3 or a trucker in Africa who is lead-footing it over a few hundred miles of washboard road. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM. |
| 20 Apr 2008 22:20:11 |
| krw |
| Re: Survey: FPGA PCB layout |
In article <6PQOj.21063$%41.8783@nlpi064.nbdc.sbc.com >, notthisjoergsch@removethispacbell.net says... > John Larkin wrote: > > On Sun, 20 Apr 2008 14:13:21 -0700, Joerg > > <notthisjoergsch@removethispacbell.net> wrote: > > > >> John Larkin wrote: > >>> On Sat, 19 Apr 2008 14:17:44 -0700, Joerg > >>> <notthisjoergsch@removethispacbell.net> wrote: > >>> > >>>> Nico Coesel wrote: > >>>>> Dave <dhschetz@gmail.com> wrote: > >>>>> > >>>>>> Does anybody out there have a good methodology for determining your > >>>>>> optimal FPGA pinouts, for making PCB layouts nice, pretty, and clean? > >>>>>> The brute force method is fairly maddening. I'd be curious to hear if > >>>>>> anybody has any 'tricks of the trade' here. > >>>>> I start thinking about how the PCB should be routed the minute I start > >>>>> to draw a schematic. I always draw components with their actual > >>>>> pin-outs. This helps to group pins together and it helps to > >>>>> troubleshoot the circuit when the prototype is on your bench (no need > >>>>> to lookup the pinouts because they are in your diagram). > >>>>> > >>>> For quad opamps like the LM324 as well? That can make a schematic harder > >>>> to read and will also cause a nightmare if the layouter wants to swap > >>>> amp A with amp C and stuff like that. > >>>> > >>>> [...] > >>> A quad opamp doesn't have 1738 pins! > >>> > >> Well, yes, I was just wondering about whether Nico really always draws > >> the physical package. Looks like he doesn't for smaller stuff. > >> > >> With 1738 pins you can only hope that the FPGA has enough routing > >> resources. That used to be a major pain in the early 90's. Don't know > >> about nowadays since other guys design the parts with the big FPGAs. And > >> I am glad I don't have to deal with BGA, at least not with large ones ... > > > > The biggest ones we use are Sparten 3's with 456 balls on 1 mm > > centers. We haven't had any routing problems so far, doing pretty > > complex stuff at 128 MHz clock rates. Our in-house BGA soldering > > yield, to date, is exactly 100%. BGAs seem to be a lot easier to > > solder reliably than fine-pitch leaded parts. Easier to inspect, too, > > since you can't inspect them at all. > > > > The latter is a concern in my field (medical). We need to be able to > inspect. The other concern is involuntary board flexing. Most of my > designs have to sustain under tortures such as freighter pilots > ploughing through a storm in the Carribean in airplanes as old as a DC-3 > or a trucker in Africa who is lead-footing it over a few hundred miles > of washboard road. > X-Rays? -- Keith < |